The present invention relates to memory devices such as ROMs, MRAMs, FeRAMs, flash memory and the like.
FIG. 1 shows a prior art memory device with individual reference sections 10, 12, 13, 14 for each core memory array 20, 22, 23, 24, respectively. Each core array 20, 22, 23, 24 may be a ROM core array having a plurality of bit lines 127 and word lines 121, the bit lines for each core array being connected to a respective multiplexer 30, 32, 33, 34 which receives column decoding signals Y0 to YM-1 and a reference signal YREF. Each core array can receive a virtual operating voltage VDD (VVDD) via a power line called a VVDD line for each column of the memory core. Upon selection of the bit line for reading out, the VVDD line is charged from a reference potential to an operating voltage VDD. The reference sections 10, 12, 13, 14 each have a bit line reference BLREF 19 and virtual VDD reference VVDDREF 18 for a respective core array. If the memory is organized in words of N bits, for example 16 bits, then for each bit output, both VVDDREF and VVDD are switched from a reference potential VSS to an operating voltage VDD. During a read operation, a bit line reference BLREF can then be used with the bit line output BL of the respective core array 20 to read the bit line output BL.
Each multiplexer 30, 32 has part of a circuitry delegated for the activation or selection of a reference column, the circuitry called a reference mulitplexer 35, 36. At the output of each bitline multiplexer 30, 32 is a respective selection/deselection logic circuit 40, 42, each providing a reference signal DLREF from the reference mux and a multiplexer output signal DL to a respective sense amplifier 50, 52.
WO2006/024403 A1 discloses a ROM memory circuit, and is hereby incorporated by reference herein.
The article “A Low Power ROM Using a Single Charge Sharing Capacitor” by Byung-Do Yang and Lee-Sup Kim shows a ROM memory circuit and is hereby incorporated by reference herein.